An integrated circuit (IC) is an electronic circuit formed using a semiconductor material, such as Silicon, as a substrate and by adding impurities to form solid-state electronic devices, such as transistors, diodes, capacitors, and resistors. Commonly known as a “chip” or a “package”, an integrated circuit is generally encased in rigid plastic, forming a “package”. The components in modern day electronics generally appear to be rectangular black plastic packages with connector pins protruding from the plastic encasement. Often, many such packages are electrically coupled so that the chips therein form an electronic circuit to perform certain functions.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A layout includes shapes that the designer selects and positions to achieve a design objective. The objective is to have the shape—the target shape—appear on the wafer as designed. However, the shapes may not appear exactly as designed when manufactured on the wafer through photolithography. For example, a rectangular shape with sharp corners may appear as a rectangular shape with rounded corners on the wafer.
Once a design layout, also referred to simply as a layout, has been finalized for an IC, the design is converted into a set of masks or reticles. A set of masks or reticles is one or more masks or reticles. During manufacture, a semiconductor wafer is exposed to light or radiation through a mask to form microscopic components of the IC. This process is known as photolithography.
A manufacturing mask is a mask usable for successfully manufacturing or printing the contents of the mask onto wafer. During the photolithographic printing process, radiation is focused through the mask and at certain desired intensity of the radiation. This intensity of the radiation is commonly referred to as “dose”. The focus and the dosing of the radiation is controlled to achieve the desired shape and electrical characteristics on the wafer.
Many semiconductor devices are planar, i.e., where the semiconductor structures are fabricated on one plane. A non-planar device is a three-dimensional (3D) device where some of the structures are formed above or below a given plane of fabrication.
Currently, a need exists for high density, high performance, memory devices that also have low power consumption. An emerging memory device technology is that of phase change memory. Phase change memory (PCM) is a type of nonvolatile random access memory (RAM). PCM exploits the behavior of a phase change material in which the phase change material is capable of transitioning between a crystalline phase and an amorphous phase responsive to an electrical current passing through the phase change material. Typically, in PCM fabrication the phase change material includes a chalcogenide compound such as germanium-antimony-tellurium (GST).
The PCM includes a region of phase change material disposed between a bottom electrode contact and a top electrode contact. The phase change material has a low resistivity when in the crystalline phase and a high resistivity when in the amorphous phase. To set the PCM in the amorphous phase, the phase change material is first melted and then quenched rapidly by applying a large electrical current pulse for short period of time leaving a region of amorphous, highly resistive material in the PCM cell. To set the PCM in the crystalline phase, a medium electrical current pulse is applied to anneal the phase change material at a temperature between the crystallization temperature and the melting temperature for a time period long enough to crystallize the phase change material having a relatively low resistivity. To read the state of the PCM, the resistivity of the cell is measured by passing a low current electrical signal through the cell which does not disturb the state of the phase change material. In addition, PCM technology has the ability to achieve a number of distinct intermediary states, thereby providing for the capability for PCM to hold multiple bits in a single cell providing for increased memory density.
Phase change memory device elements can be constructed in several ways. In one implementation, a planar phase change material film is deposited and pillars are lithographically defined and pattered into the phase change material by a plasma etching. Drawbacks of such implementations include that the phase change materials are sensitive to processing such as etching, cleaning, and encapsulation and can be damaged during device fabrication. In another implementation, patterned holes are formed in a dielectric material and phase change material is grown inside the holes. This implementation provides a good alternative to phase change memory pillars to avoid pillar damaged by post-processing. However a drawback of this implementation is that it is a large challenge to completely fill nanometer-sized, high aspect ratio holes required for high density memory elements.
Phase change materials can be deposited in number of ways such as by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and metalorganic chemical vapor deposition (MOCVD). However, in all cases filling nanometer-sized, high aspect ratio holes are a challenge. Atomic layer deposition (ALD) is another technique that may be used to fill nanometer-sized, high aspect ratio holes. However, ALD has disadvantages in that layer-by-layer growth is slow and precursors can remain in the film after deposition. CVD processes in general are faster, but run into the incomplete fill problems. In addition, even layer-by-layer growth cannot completely fill re-entrant hole profiles. It has been found that ALD of phase change material proceeds faster and more uniformly on a metal seeding layer as compared to a dielectric seeding layer, so it is beneficial to grow the phase change material on a metal layer lining holes in the dielectric (i.e., a metal liner). Having a metal liner also has shown benefits to electrical resistance drift mitigation in PCM device operation.
Existing solutions for CVD deposition of phase change material, such as GST, on a metal liner exhibit a number of drawbacks. CVD deposition of amorphous GST on a metal liner can provide completely filled holes after deposition, but undergoes a volume shrinkage that introduces voids in the phase change material. CVD deposition of crystalline GST on a metal liner provides for crystal grain growth that is directional from nucleation sites, allowing for blocking and void formation within the phase change material. CVD deposition of nanocrystalline GST on a metal liner provides for the growth of small grains that allows possible complete filling of the holes. However, voids due to blocking still occur and the process window for nanocrystalline grain growth is very small.
The illustrative embodiments recognize that the present methods and techniques for growing phase change material in high aspect ratio dielectric pores for fabrication of a semiconductor device, such as a PCM device, presents the above described problems. Illustrative embodiments described herein provide for selective phase change material growth in high aspect ratio dielectric pores for semiconductor device fabrication providing a phase change memory device that is small (e.g., 20 nm critical dimension and smaller), has low reset current, has electrical resistance drift mitigation, and is void-free across the wafer yield.